Synthesis for Full Testability of Partitioned Combinational Circuits Using Boolean Diierential Calculus
نویسندگان
چکیده
| Synthesis for testability has been taken as an important topic of research and application. Tools for synthesis of fully testable circuits have been developed. These design tools are faced with an ever increasing complexity. Methods to partition large logics into parts and synthesis of each sublogic independently have been provided from different points of view recently. However, a large circuit may be no longer testable even if all sublogics are designed for full testability. To make large circuits fully testable, we propose a method of synthesis for full testability of two-level-partitioned circuits , in which full testability is obtained by changing the behavior descriptions of each module using some information about the other module without changing the global behavior. We also prove the termination of our algorithm. Some experimental results have been included in this paper.
منابع مشابه
Behavioral to Structural Translation in ESOP Form
A translator for behavioral to structural descriptions of combinational logic circuits is presented. The input is in the form of a Boolean equation using V erilog syntax and the output is a V erilog net-list. The structure of the output circuit is in terms of an Exclusive-OR Sum-of-Products (ESOP) form which is noted for ease of testability and a reduced number of logic gates as compared to tra...
متن کاملAnalysis of Incomplete Circuits using Dependency Quantified Boolean Formulas
We consider Dependency Quantified Boolean Formulas (DQBFs), a generalization of Quantified Boolean Formulas (QBFs), and demonstrate that DQBFs are a natural calculus to exactly express the realizability problem of incomplete combinational and sequential circuits with an arbitrary number of (combinational or bounded-memory) black boxes. In contrast to usual approaches for controller synthesis, r...
متن کاملSynthesis of robust delay-fault-testable circuits: theory
Correct operation of synchronous digital circuits requires propagation delays of all sensitizable paths in the circuit to be smaller than a speciied limit. Physical defects and processing variations in integrated circuits can aaect the temporal behavior of a circuit without altering the logical behavior. These defects are called delay faults. In order to design, and especially to synthesize, hi...
متن کاملDYTEST: A Self-learning Algorithm Using Dynamic Testability Heasures to Accelerate Test Generation
This paper presents a self-learning algorithm using a dynamic testability measure to accelerate test generation. It also introduces the concepts o f full logic value label backward implication, the dependent backtrack and K-limited backtracks. Results indicating a high fault coverage are also presented for ten benchmark combinational circuits.
متن کاملModeling and Synthesis of Combinational Logic Circuits - a Power Dissipation
With the advent of deep submicron technology, the number of transistors in a chip has increased very rapidly. As the complexity of VLSI circuits increases fast, the automation of the VLSI design has become very crucial not only to reduce design time and cost, but also to improve design quality. There are several criteria to measure design quality: area, delay, testability and power consumption....
متن کامل